发明名称 MULTILEVEL VIA PLACEMENT WITH IMPROVED YIELD IN DUAL DAMASCENE INTERCONNECTION
摘要 A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.
申请公布号 US2015186588(A1) 申请公布日期 2015.07.02
申请号 US201414577195 申请日期 2014.12.19
申请人 Texas Instruments Incorporated 发明人 HONG Qi-Zhong
分类号 G06F17/50;H01L23/522 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method of operating a computer system to improve interconnect reliability in an integrated circuit comprising the steps of: retrieving via layout data associated with a top via layer and a bottom via layer of the integrated circuit wherein the top and the bottom vias are coupled to an intermediate interconnect level; and performing a first modification of via layout data of at least one of the top via layer and the bottom via layer to form an R-stack; and storing the first modification of the via layout data in the computer.
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