| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an information processing system that shortens a startup time at a system reset. <P>SOLUTION: A function module 1 of a plurality of function modules resets a PLL circuit 10 and a signal processing section 12 in response to a system reset signal and then cancels the reset to the PLL circuit 10. If an internal clock signal generated in the PLL circuit 10 after the reset cancellation is not phase-locked to a system clock signal, a first startup state signal indicating that a startup is in process is supplied to a function module 2. If it is phase-locked, on the other hand, a second startup state signal indicating that the startup is complete is supplied to the function module 2, and the reset to the signal processing section 12 is canceled. The function module 2 resets a PLL circuit 20 and a signal processing section 22 in response to the first startup state signal. The reset to the PLL circuit 20 is canceled in response to the second startup state signal, and the reset to the signal processing section 22 is canceled in the event of phase locking after the reset cancellation. <P>COPYRIGHT: (C)2013,JPO&INPIT |
