Apparatus and method for synchronizing and providing a glitch-free clock

摘要

In accordance with an exemplary embodiment, an apparatus, a computer product and a method are provided for selecting among asynchronous clocks and for generating a clock without glitch to the output. The apparatus comprises two or more synchronizer units, each connected to an assigned clock signal. Each synchronizer unit receives a clock select signal and a status signal of the other clock(s). It generates a synchronized enable request signal and a synchronized status signal of the other clock(s) to a processor or a state machine. In response to the synchronized enable request signal and the synchronized status signal of the other clock(s), the processor generates an enable signal to a clock gate and a status output signal to the other synchronizer unit(s). The enable signal controls the clock gate which enables or disables the clock signal to an output.