| 摘要 |
<p>A disclosed display device includes a display panel (30) with data lines (34) and gate lines (35), the gate lines including odd-numbered gate lines and even-numbered gate lines. The display device also includes a timing controller (31) to generate a gate output enable signal (GOE), and a gate output enable signal division circuit (300) to extract odd-numbered high logic periods of the gate output enable signal (GOE) to output a first gate output enable signal (GOE_O) and to extract even-numbered high logic periods of the gate output enable signal (GOE) to output a second gate output enable signal (GOE_E). The display device further includes a gate driver (331-335) to supply a first gate pulse (GO_O) to an odd-numbered gate line in response to the first gate output enable signal (GOE_O) and a second gate pulse (GO_E) to an even-numbered gate line in response to the second output enable signal (GOE_E).</p> |
