Self aligned patterning with multiple resist layers

摘要

A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.

主权项

1. A method for fabricating an integrated circuit, the method comprising:
forming a first patterned resist layer onto a substrate; forming a spacer layer over the first patterned resist layer such that spacer forms on side walls of features of the first patterned resist layer; forming a second patterned resist layer over the spacer layer and depositing a masking layer; removing a portion of the second patterned resist layer to expose the first patterned resist layer; removing the remaining first and second resist layers; and exposing the substrate.