| 发明名称 | Mechanisms to accelerate transactions using buffered stores | ||
| 摘要 | In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | ||
| 申请公布号 | US9069670(B2) | 申请公布日期 | 2015.06.30 |
| 申请号 | US201213658212 | 申请日期 | 2012.10.23 |
| 申请人 | Intel Corporation | 发明人 | Adl-Tabatabai Ali-Reza;Ni Yang;Saha Bratin;Bassin Vadim;Sheaffer Gad;Callahan David;Gray Jan |
| 分类号 | G06F12/08;G06F9/46;G06F12/10;G06F9/52;G06F9/30 | 主分类号 | G06F12/08 |
| 代理机构 | Trop, Pruner & Hu, P.C. | 代理人 | Trop, Pruner & Hu, P.C. |
| 主权项 | 1. A method comprising: executing a transactional memory (TM) transaction of an atomic section of code in a first thread within a processor; during the TM transaction, buffering a block of data in a first buffer of a cache memory of the processor; and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. | ||
| 地址 | Santa Clara CA US | ||