Addressing Auto address Assignment and Auto-Routing in NAND Memory Network

摘要

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

主权项

1. A non-volatile memory system comprising:
a memory section including
a plurality of non-volatile circuits each having a first set of bus connections and a second set of bus connections; anda bus structure connecting the memory circuits in a tree-type of arrangement that includes a front section, the front section having a series of multiple tiers in which, for each tier except the last in the series of the front section, the second set of bus connections of memory circuits in each tier branch out and connect to the first set of bus connections of a set one or more memory circuits of the subsequent tier in the series, and where the first set of bus connections of the one of more memory circuits of the first tier are connected to a corresponding branch from an input bus section; and a controller circuit connected to the input bus section, wherein the controller circuit addresses the memory circuits according to a tier address that identities the tier to which an addressed memory circuit belongs and, for the identified tier and each preceding tier, a sub-address that identifies the branch to which the memory circuit belongs.