| 发明名称 |
2-D Gather Instruction and a 2-D Cache |
| 摘要 |
A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image. |
| 申请公布号 |
US2015178217(A1) |
申请公布日期 |
2015.06.25 |
| 申请号 |
US201514635403 |
申请日期 |
2015.03.02 |
| 申请人 |
Ginzburg Boris;Margulis Oleg |
发明人 |
Ginzburg Boris;Margulis Oleg |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
a decode unit to decode a two-dimensional (2-D) gather instruction; an execution unit to perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor; and a 2-D cache to store the one or more sub-blocks of data in multiple cache lines, support access to more than one cache line in a single processing cycle, and preserve a two-dimensional structure of the 2-D image, wherein the 2-D cache includes a plurality of sets and a plurality of ways. |
| 地址 |
Haifa IL |
