Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

摘要

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

主权项

1. A method for fabricating stacked microelectronic packages, comprising:
bonding upper and lower package layers in a stacked relationship, each package layer including a molded package layer body, a microelectronic device embedded within the molded package layer body, and package edge conductors electrically coupled to the microelectronic device and extending to at least one sidewall of the package layer; after bonding the upper and lower package layers, applying a flowable conductive material on sidewalls of the upper and lower package layers and contacting the package edge conductors; and removing selected portions of the flowable conductive material to define, at least in part, a plurality of sidewall conductors electrically coupled to the package edge conductors and electrically interconnecting the microelectronic devices within the upper and lower package layers wherein removing comprises forming openings extending vertically through the flowable conducive material to electrically isolate adjacent ones of the sidewall conductors interconnecting the microelectronic devices within the upper and lower package layers.