Timing logic for memory array

摘要

Among other things, techniques and systems are provided for devising a schedule for performing read/write operations on a memory cell. A control signal is provided to timing logic. Using one or more properties of the control signal, such as a voltage property, the timing logic is configured to adjust a time window during which at least one of a read operation or a write operation is performed within a cycle. In this way, the timing logic affects a dynamic switch between an early-read operation, a late-read operation, an early-write operation, a late-write operation, a read-then-write operation, and a write-then-read operation between cycles. In some embodiments, the memory cell for which the schedule is devised is an SRAM cell, such as a six-transistor SRAM cell.

主权项

1. A control logic for a memory cell, comprising:
timing logic configured to:
receive a clock signal indicative of clock cycles;receive at least one of:
a write enable signal specifying whether to perform write operations during respective clock cycles; ora read enable signal specifying whether to perform read operations during respective clock cycles;receive a control signal specifying a timing for performing at least one of the read operations or the write operations during the respective clock cycles; andadjust, between clock cycles, a start time of at least one of a read operation or a write operation based upon the control signal.