Secondary bit line equalizer

摘要

Systems, methods, and other embodiments associated with bit line equalization are described. Systems and methods described herein provide secondary bit line equalization for embedded memory systems to reduce equalization time and improve memory performance. The reduction in equalization time is accomplished by adding a secondary equalizer in addition to a standard primary equalizer for a column of memory cells.

主权项

1. A memory, comprising:
a bit line; a complementary bit line; a column of memory cells, wherein each memory cell is electrically connected to the bit line and the complementary bit line; a first circuit connected between the bit line and the complementary bit line proximate a first end of the column of memory cells, wherein the first circuit is enabled by a first signal to electrically connect the bit line and the complementary bit line; a second circuit connected between the bit line and the complementary bit line proximate a second end of the column of memory cells that is opposite the first end, wherein the second circuit is enabled by a second signal to electrically connect the bit line and the complementary bit line; and wherein the first signal and the second signal are generated based on a write enable signal that is provided to the column of memory cells when a write operation is performed on a memory cell in the column, such that during a time period following a write operation, both the first circuit and the second circuit connect the bit line to the complementary bit line.