Method and system for optimizing prefetching of cache memory lines

摘要

A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.

主权项

1. An apparatus comprising:
a processing unit comprising:
a data cache memory having a plurality of cache memory lines;a tag memory having a first partition and a second partition, wherein the first partition comprises entries associated with cache memory lines having an even set index, and wherein the second partition comprises entries associated with cache memory lines having an odd set index;a processing core; anda cache memory; the processing unit to:
determine that data of a vector memory operand is cached in two adjacent cache memory lines based on a size of the vector memory operand and a starting address of a first byte and a second byte of the vector memory operand;determine, based on a set index in a linear address of the vector memory operand, that the two adjacent cache memory lines comprise a first cache memory line with an even set index and a second cache memory line with an odd set index; andpre-fetch, using a single data cache memory execution slot responsive to the determination that the two adjacent cache memory lines comprise the first cache memory line with the even set index and the second cache memory line with the odd index, the first cache memory line from the first partition and the second cache memory line from the second partition.