DRAM ADDRESS PROTECTION

摘要

In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.

主权项

1. A memory controller comprising:
a data interface coupled to a memory via a data bus, the data interface configured to write data to an address in the memory; an address interface coupled to the memory via an address bus, the address interface to provide the address to the memory; an error code generation module configured to generate an error code based on a function of the data and the address, the error code being a combination of a check bit code and a gray code; and an error interface configured to, responsive to a write request for the data, store the error code at a portion of the memory corresponding to the address.