发明名称 |
SYSTEM AND METHODS FOR CACHING A SMALL SIZE I/O TO IMPROVE CACHING DEVICE ENDURANCE |
摘要 |
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the cache-lines comprises a plurality of sub-cache lines. Each of the plurality of cache-lines and each of the plurality of sub-cache lines is associated with meta-data indicating one or more of a dirty state and an invalid state. The controller is connected to the memory and configured to (i) recognize sub-cache line boundaries and (ii) process the I/O requests in multiples of a size of said sub-cache lines to minimize cache-fills. |
申请公布号 |
US2015169458(A1) |
申请公布日期 |
2015.06.18 |
申请号 |
US201314132440 |
申请日期 |
2013.12.18 |
申请人 |
LSI Corporation |
发明人 |
Purkayastha Saugata Das;Bert Luca;Simionescu Horia;Sampathkumar Kishore Kaniyar;Ish Mark |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a memory configured to (i) implement a cache and (ii) store meta-data, said cache comprising one or more cache windows, each of said one or more cache windows comprising (i) a plurality of cache-lines configured to store information and (ii) each of said cache-lines comprises a plurality of sub-cache lines, wherein each of said plurality of cache-lines and each of said plurality of sub-cache lines is associated with meta-data indicating one or more of a dirty state and an invalid state; and a controller connected to said memory and configured to (i) recognize sub-cache line boundaries and (ii) perform processing of I/O requests in multiples of a size of said sub-cache lines to minimize cache-fills. |
地址 |
San Jose CA US |