发明名称 |
MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND COMPUTER PRODUCT |
摘要 |
A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present. |
申请公布号 |
US2015169456(A1) |
申请公布日期 |
2015.06.18 |
申请号 |
US201514630400 |
申请日期 |
2015.02.24 |
申请人 |
FUJITSU LIMITED |
发明人 |
SUZUKI Takahisa;Yamashita Koichiro;Yamauchi Hiromasa;Kurihara Koji |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Kawasaki-shi JP |