| 摘要 |
<p>A semiconductor memory has a memory cell array having a plurality of real word lines, a plurality of redundant word lines, a plurality of bit lines crossing with the real and redundant word lines, a plurality of memory cells provided at crossing section of the real and redundant word lines and the bit lines, and a row selection circuit for selecting the real word line or the redundant word line in accordance with a row address being supplied. The row selection circuit selects the real word line or the redundant word line at an ordinary operation, and multi-selects the redundant word lines at a first test mode.</p> |
