Nonvolatile semiconductor memory device and method for manufacturing same

摘要

According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body having a gate insulating film, a first charge storage layer, a first insulating film, a second charge storage layer, and a second insulating film, a second element isolation region, a bottom and at least part of a side portion of the second element isolation region being in contact with the semiconductor substrate in the peripheral portion; and a second stacked body, a third insulating film, a first layer, a fourth insulating film, a second layer, and the second insulating film are stacked in this order from the semiconductor substrate side between the semiconductor substrate and the control gate electrode in the second stacked body in the peripheral portion, a side portion of the second stacked body being covered with the second insulating film.

主权项

1. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate provided in a memory cell portion and in a peripheral portion at a periphery of the memory cell portion; a control gate electrode provided on an upper side of the semiconductor substrate and the control gate electrode extending in a first direction; a first element isolation region, a bottom and part of a side portion of the first element isolation region being in contact with the semiconductor substrate, the first element isolation region extending in a second direction crossing the first direction, and the first element isolation region separating a surface layer of the semiconductor substrate into a plurality of semiconductor regions in the memory cell portion; a first stacked body, a gate insulating film, a first charge storage layer, a first insulating film, a second charge storage layer, and a second insulating film are stacked in this order from the semiconductor region side in the first stacked body, the first stacked body being positioned in a position, each of the plurality of semiconductor regions and the control gate electrode cross each other in the position in the memory cell portion; a second element isolation region, a bottom and at least part of a side portion of the second element isolation region being in contact with the semiconductor substrate in the peripheral portion; and a second stacked body, a third insulating film, a first layer, a fourth insulating film, a second layer, and the second insulating film are stacked in this order from the semiconductor substrate side between the semiconductor substrate and the control gate electrode in the second stacked body in the peripheral portion, a side portion of the second stacked body being covered with the second insulating film.