发明名称 |
Semiconductor device including flip-flop and logic circuit |
摘要 |
To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal. |
申请公布号 |
US9059689(B2) |
申请公布日期 |
2015.06.16 |
申请号 |
US201414160774 |
申请日期 |
2014.01.22 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Kato Kiyoshi;Uesugi Wataru |
分类号 |
H03K5/04;H03K5/06;H03K5/05;H03K5/00 |
主分类号 |
H03K5/04 |
代理机构 |
Fish & Richardson P.C. |
代理人 |
Fish & Richardson P.C. |
主权项 |
1. A semiconductor device comprising:
a first transistor; a circuit including a second transistor; a flip-flop; and a logic circuit, wherein a channel of the first transistor is included in an oxide semiconductor layer, wherein an output of the logic circuit is input to a gate of the first transistor, wherein a first signal is input to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein a first clock signal is input to the circuit, wherein a second clock signal is output from the circuit to the flip-flop, wherein a second signal and an output signal of the flip-flop are input to the logic circuit, and wherein a timing of the second clock signal is different from a timing of the first clock signal. |
地址 |
Atsugi-shi, Kanagawa-ken JP |