发明名称 |
Clock data recovery circuit and clock data recovery method |
摘要 |
A clock data recovery circuit includes: a phase detector circuit configured to generate a phase detection signal indicating a first detection result between a phase of a reception data signal and a phase of a first clock signal; a clock signal generation circuit configured to generate the first clock signal and a second clock signal based on the phase detection signal, the second clock signal having a frequency substantially equal to a frequency of the first clock signal, a phase difference between the first clock signal and the second clock signal being less than 180°; a phase combining circuit configured to combine the first clock signal and the second clock signal in accordance with a phase relation and generate a recovered clock signal; and a recovered data generation circuit configured to sample the reception data signal and generate a recovered data signal based on the recovered clock signal. |
申请公布号 |
US9059837(B1) |
申请公布日期 |
2015.06.16 |
申请号 |
US201414541197 |
申请日期 |
2014.11.14 |
申请人 |
FUJITSU LIMITED |
发明人 |
Tsunoda Yukito;Shibasaki Takayuki |
分类号 |
H03D3/24;H04L7/033;H04L7/00 |
主分类号 |
H03D3/24 |
代理机构 |
Staas & Halsey LLP |
代理人 |
Staas & Halsey LLP |
主权项 |
1. A clock data recovery circuit comprising:
a phase detector circuit configured to generate a phase detection signal indicating a first detection result between a phase of a reception data signal and a phase of a first clock signal; a clock signal generation circuit configured to generate the first clock signal and a second clock signal based on the phase detection signal, the second clock signal having a frequency substantially equal to a frequency of the first clock signal, a phase difference between the first clock signal and the second clock signal being less than 180°; a phase combining circuit configured to combine the first clock signal and the second clock signal in accordance with a phase relation and generate a recovered clock signal; and a recovered data generation circuit configured to sample the reception data signal and generate a recovered data signal based on the recovered clock signal. |
地址 |
Kawasaki JP |