发明名称 Cache arrangement
摘要 A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.
申请公布号 US9058283(B2) 申请公布日期 2015.06.16
申请号 US201213560559 申请日期 2012.07.27
申请人 STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED 发明人 Ryan Stuart;Jones Andrew Michael
分类号 G06F12/00;G06F12/08 主分类号 G06F12/00
代理机构 Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A. Attorneys at Law 代理人 Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A. Attorneys at Law
主权项 1. A first cache arrangement comprising: an input configured to receive a read memory request; a first cache memory for storing data; an output configured to provide a response to the read memory request; and a first cache controller configured to determine whether said first cache memory includes stored data corresponding to the read memory request,retrieve the stored data corresponding to the read memory request from said first cache memory when said first cache memory includes the stored data corresponding to the read memory request,send the read memory request to a second cache arrangement when said first cache memory does not include the stored data corresponding to the read memory request, the second cache arrangement comprising a pre-fetch engine configured to, independently from the first cache controller, perform at least one pre-fetch of the stored data based upon the read memory request, a second cache memory, and a second cache controller coupled to the pre-fetch engine and the second cache memory, the second cache controller configured to, independently from said first cache controller, allocate the stored data from the at least one pre-fetch in the second cache memory and invalidate the stored data allocated from the at least one pre-fetch when the stored data is for the read memory request,receive the stored data corresponding to the read memory request from the second cache arrangement when the second cache arrangement includes the stored data corresponding to the read memory request,receive the stored data corresponding to the read memory request from a memory via the second cache arrangement when the second cache arrangement does not include the stored data corresponding to the read memory request and without an allocation for the stored data being made in the second cache arrangement, andsend the stored data via the output.
地址 Marlow Bucks GB