发明名称 |
CLOCK GENERATION CIRCUIT |
摘要 |
The present technique relates to a clock generation circuit including a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal, a filter circuit configured to suppress a high frequency component in the phase difference signal, an output circuit configured to modulate the phase difference signal in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal, and a frequency dividing circuit configured to divide a frequency of the output clock signal, at a predetermined frequency dividing ratio, and feed it back to the phase comparison circuit. |
申请公布号 |
US2015162917(A1) |
申请公布日期 |
2015.06.11 |
申请号 |
US201414539293 |
申请日期 |
2014.11.12 |
申请人 |
Sony Corporation |
发明人 |
Tsukuda Yasunori |
分类号 |
H03L7/06;H03K3/013;H03M3/00;H03K21/02 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
1. A clock generation circuit comprising:
a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal which have been received, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal; a filter circuit configured to suppress a high frequency component, of which frequency is higher than a predetermined cutoff frequency, in the phase difference signal; an output circuit configured to modulate the phase difference signal, of which high frequency component is suppressed, in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal; and a frequency dividing circuit configured to divide a frequency of the output clock signal, which has been output, at a predetermined frequency dividing ratio, and feed the output clock signal back to the phase comparison circuit as the feedback signal. |
地址 |
Tokyo JP |