A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.
申请公布号
WO2015084971(A1)
申请公布日期
2015.06.11
申请号
WO2014US68394
申请日期
2014.12.03
申请人
RAMBUS INC.;SEKAR, DEEPAK CHANDRA;HAUKNESS, BRENT S.;BATEMAN, BRUCE L.
发明人
SEKAR, DEEPAK CHANDRA;HAUKNESS, BRENT S.;BATEMAN, BRUCE L.