STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS

摘要

A circuit design checker receives a circuit design. The circuit design can include a first set of one or more logic components in a first clock domain and a second set of one or more logic components in a second clock domain. The clock domain checker identifies a first subset of the second set of one or more logic components that receive one or more asynchronous clock domain crossings. The circuit design is traversed to determine whether a subset of the one or more asynchronous clock domain crossings does not pass through a signal having an attribute indicating that the signal is intended to be part of the one or more asynchronous clock domain crossings. If such a crossing exists, an error is indicated for the circuit design.

主权项

1. A method for checking circuit designs with asynchronous clock domain crossings, the method comprising:
receiving a circuit design, the circuit design including a first set of one or more logic components in a first clock domain and a second set of one or more logic components in a second clock domain; identifying, by one or more processors, a first subset of the second set of one or more logic components that receive one or more asynchronous clock domain crossings; traversing, by the one or more processors, at least a portion of the circuit design to determine whether a subset of the one or more asynchronous clock domain crossings does not pass through a signal having an attribute indicating that the signal is intended to be part of the one or more asynchronous clock domain crossings; and indicating an error for the circuit design in response to determining that the subset of the one or more asynchronous clock domain crossings has at least one member.