发明名称 Data processing apparatus having a cache
摘要 An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.
申请公布号 GB201507191(D0) 申请公布日期 2015.06.10
申请号 GB20150007191 申请日期 2015.04.28
申请人 ARM LIMITED 发明人
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