Test circuit allowing precision analysis of delta performance degradation between two logic chains

摘要

A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter.

主权项

1. An integrated circuit containing a test circuit, the test circuit comprising:
an oscillator having an oscillator output node; a calibration divider circuit having a calibration divider input node and a calibration divider output node, such that said calibration divider input node is connected to said oscillator output node; a starter divider circuit having a starter divider input node and a starter divider output node, such that said starter divider input node is connected to said oscillator output node; a test gate chain containing a number, NTEST, of test gates, wherein said test gates are connected in series between a test gate chain input node and a test gate chain output node, and wherein said test gate chain input node is connected to said starter divider output node; a reference gate chain containing a number, NREF, of reference gates, wherein said reference gates are connected in series between a reference gate chain input node and a reference gate chain output node, and wherein said reference gate chain input node is connected to said starter divider output node; a start/stop decoder circuit including a test input, a reference input, a start output and a stop output, wherein said test input is connected to said test gate chain output of, wherein said reference input is connected to said reference gate chain output; and a counter circuit including a start input, a stop input, a clock input and a plurality of count outputs, wherein said start input is connected to said start output of said start/stop decoder circuit, said stop input is connected to said stop output of said start/stop decoder circuit, said clock input is connected to said oscillator output node.