发明名称 IMAGE PROCESSING APPARATUS, AND CONTROL METHOD AND PROGRAM OF THE SAME
摘要 PROBLEM TO BE SOLVED: To solve a problem that RAM access for reconfiguration is kept waiting during real-time processing to decrease processing efficiency when circuit configuration information is stored in a high-speed RAM and dynamic reconfiguration is performed by using the RAM. ! SOLUTION: In an image processing apparatus which comprises an FPGA in which at least a part of a circuit is dynamically reconfigured, a ROM 104 for storing circuit configuration information for reconfiguring at least a part of the circuit in the FPGA, and a RAM 111, capable of reading at a higher speed than the ROM 104, for storing circuit configuration information stored in the ROM 104, at least a part of the FPGA is reconfigured depending on a job to execute to a circuit which can execute processing necessary for the job by using the circuit configuration information, and the FPGA is reconfigured by using the circuit configuration information stored in the RAM 111 when real-time processing using the RAM 111 is not in executi
申请公布号 JP2015106751(A) 申请公布日期 2015.06.08
申请号 JP20130246677 申请日期 2013.11.28
申请人 CANON INC 发明人 OBAYASHI YOSUKE
分类号 H04N1/00;B41J29/38;G03G21/00 主分类号 H04N1/00
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