ADHESIVE PATTERN FOR ADVANCE PACKAGE RELIABILITY IMPROVEMENT

摘要

The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

主权项

1. An integrated chip (IC) package, comprising:
an integrated chip (IC) die coupled to an underlying substrate by a plurality of electrically conductive bonding structures; a first adhesive layer having a first Young's modulus and disposed onto the substrate at a first plurality of positions surrounding the IC die; a second adhesive layer having a second Young's modulus, different than the first Young's modulus, and disposed onto the substrate at a second plurality of positions surrounding the IC die; and a lid affixed to the substrate by the first and second adhesive layers and configured to extend to a position overlying the IC die.