The present invention relates to a clock data recovery circuit (600) comprising a data sampling circuit (601) to generate data samples of an input data signal (D N ) response to a first clock signal (210); an edge sampling circuit (607) to generate edge samples of the input data signal in response to a second clock signal (610); and a clock recovery circuit (605) coupled to receive the edge samples and the data samples, the clock recovery circuit being configured to adjust a phase of the second clock signal according to the state of one of the edge samples upon determining that a sequence of at least three of the data samples matches at least one sample pattern of a plurality of predetermined sample patterns.
申请公布号
EP2259519(B1)
申请公布日期
2015.06.03
申请号
EP20100175167
申请日期
2004.04.09
申请人
RAMBUS INC.
发明人
STOJANOVIC, VLADIMIR, M.;HOROWITZ, MARC, A.;ZERBE, JARED, L.;BESSIOS, ANTHONY;HO, ANDREW, C., C.;WEI, JASON , C.;TSANG, GRACE;GARLEPP, BRUNO, W.