| 摘要 |
A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line. |
| 主权项 |
1. A pixel structure, comprising:
a scan line and at least one data line; at least one active device, electrically connected to the scan line and the at least one data line; at least one pixel electrode, electrically connected to the at least one active device; at least one capacitor electrode line, located underneath the at least one pixel electrode; at least one semi-conductive pattern layer, disposed between the at least one capacitor electrode line and the at least one pixel electrode, wherein the at least one semi-conductive pattern layer is electrically connected to the at least one pixel electrode; at least one storage electrode pattern layer, disposed between the at least one capacitor electrode line and the at least one pixel electrode, wherein the at least one storage electrode pattern layer is electrically connected to the at least one pixel electrode, and the at least one storage electrode patter layer does not cover the at least one semi-conductive pattern layer; and at least one dielectric layer, disposed between the at least one capacitor electrode line and the at least one pixel electrode, and located between the at least one semi-conductive pattern layer and the at least one capacitor electrode line, and located between the at least one storage electrode pattern layer and the at least one capacitor electrode line and wherein the at least one capacitor electrode line and the at least one pixel electrode having a first overlap region not overlapped with the at least one semi-conductive pattern layer and the at least one storage electrode pattern layer constitute a first storage capacitor having a first storage capacitance, the at least one semi-conductive pattern layer and the at least one capacitor electrode line having a second overlap region constitute a second storage capacitor having a second storage capacitance, and the at least one storage electrode pattern layer and the at least one capacitor electrode line having a third overlap region not overlapped with the at least one semi-conductive pattern layer constitute a third storage capacitor having a third storage capacitance, and wherein a total storage capacitance is the sum of the first storage capacitance, the second storage capacitance and the third storage capacitance, and the second storage capacitance occupies 30%-80% of the total storage capacitance, and each of the first storage capacitance, the second storage capacitance, and the third storage capacitance is larger than zero. |
