发明名称 |
Semiconductor memory device and control method of the same |
摘要 |
A semiconductor memory device includes a plurality of memory cells and a control circuit configured to apply a program voltage of an initial level to a control electrode of a selected memory cell and then of an increased level a number of times, each time without decreasing the program voltage applied to the control electrode, prior to executing a program verifying operation on the selected memory cell. In addition, the control circuit may further be configured to apply an erase voltage of an initial level to a control electrode of a selected memory cell and then of an increased level a number of times, each time without decreasing the erase voltage applied to the control electrode, prior to executing an erase verifying operation on the selected memory cell. |
申请公布号 |
US9047962(B2) |
申请公布日期 |
2015.06.02 |
申请号 |
US201313786003 |
申请日期 |
2013.03.05 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Ishii Hiroyuki |
分类号 |
G11C16/34;G11C16/10;G11C16/12;G11C16/14;G11C16/04 |
主分类号 |
G11C16/34 |
代理机构 |
Patterson & Sheridan, LLP |
代理人 |
Patterson & Sheridan, LLP |
主权项 |
1. A semiconductor memory device, comprising:
a plurality of memory cells; and a control circuit configured to apply a program voltage of an initial level to a first line electrically connected to a control electrode of a selected memory cell, and then of an increased level a number of times, each time without decreasing the program voltage applied to the first line, and execute a first verifying operation to apply a voltage that is lower than the program voltage of the initial level to the first line when the program voltage has been increased a first number of times. |
地址 |
Tokyo JP |