Low-power encryption apparatus and method

摘要

An encryption apparatus and method that provide a mobile fast block cipher algorithm that supports low-power encryption. The encryption apparatus includes a user interface unit, a key scheduler unit, an initial conversion unit, a round function processing unit, and a final conversion unit. The user interface unit receives plain text to be encrypted and a master key. The key scheduler unit generates a round key from the master key. The initial conversion unit generates initial round function values from the plain text. The round function processing unit repeatedly processes a round function using the round key and the initial round function values. The final conversion unit generates ciphertext from the resulting values of the round function processed in a final round by the round function processing unit.

主权项

1. An encryption apparatus comprising:
a user interface circuit configured to receive plain text to be encrypted and a master key, the plain text including a plurality of consecutive sub-plain texts; a key scheduler circuit configured to generate a round key RKi from the master key, the round key being formed by consecutively arranging a plurality of sub-round keys; an initial conversion circuit configured to generate initial round function values Xo from the sub-plain texts of the plain text; a round function processing circuit configured to repeatedly process a round function using the round key and the initial round function values and compute resulting values Xi of the round function by performing XOR, addition and rotation operations on the sub-round keys of the round key RKi and previous resulting values Xi−1; and a final conversion circuit configured to generate ciphertext from resulting values of the round function processed in a final round by the round function processing circuit, wherein the round function processing circuit computes Xi+1[0] using Equation Xi+1[0]←ROL9((Xi [0]⊕RKi[0])+(Xi[1]⊕RKi[1])), computes Xi+1[1] using Equation Xi+1[1]←ROR5((Xi[1]⊕RKi[2])+(Xi[2]⊕RKi[3])), computes Xi+1[2] using Equation Xi+1[2]←ROR3((Xi[2]⊕RKi[4])+(Xi[3]⊕RKi[5])), and computes Xi+1[3] using Equation Xi+1[3]←Xi[0], wherein Xi[0], Xi[1], Xi[2] and Xi[3] denote the results of the round function in an (i−1)-th round, ⊕ denotes an XOR operation, + denotes a modulo 232 addition operation, ROL a (x) denotes a function of circularly shifting value x having a length of 32 bits to the left by “a” bits and outputting the resulting value, and ROR a(x) denotes a function of circularly shifting value x having a length of 32 bits to the right by “a” bits and outputting the resulting value.