Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies

摘要

A method for forming a CMOS integrated circuit device, the method including; providing a semiconductor substrate, forming a gate layer overlying the semiconductor substrate, patterning the gate layer to form NMOS and PMOS gate structures including edges; forming a first dielectric layer overlying the NMOS and PMOS gate structures to protect the NMOS and PMOS gate structures including the edges, forming a first masking layer overlying a first region adjacent the NMOS gate structure; etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure, and depositing a silicon germanium material into the first source and drain regions to cause the channel region between the first source and drain regions of the PMOS gate structure to be strained in a compressive mode.

主权项

1. A method for forming a CMOS integrated circuit device, the method comprising:
providing a semiconductor substrate; forming a gate layer overlying the semiconductor substrate; patterning the gate layer to form an NMOS gate structure including edges and a PMOS gate structure including edges; forming a first dielectric layer overlying the NMOS gate structure to protect the NMOS gate structure including the edges and overlying the PMOS gate structure to protect the PMOS gate structure including the edges; forming a first masking layer overlying a first region adjacent the NMOS gate structure; etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure; and depositing a silicon germanium material into the first source region and the first drain region to cause the channel region between the first source region and the first drain region of the PMOS gate structure to be strained in a compressive mode; forming a second dielectric layer after depositing the silicon germanium material, the second dielectric layer overlying the NMOS gate structure and the PMOS gate structure to protect the deposited silicon germanium material, the PMOS gate structure including the edges, and the NMOS gate structure including the edges; forming a second masking layer overlying a second region adjacent the PMOS gate structure; etching a second source region and a second drain region adjacent to the NMOS gate structure using the second masking layer as a protective layer for the second region adjacent the PMOS gate structure; and depositing silicon carbide material into the second source region and the second drain region to cause a channel region between the second source region and the second drain region of the NMOS gate structure to be strained in a tensile mode.