| 发明名称 |
MERGING LITHOGRAPHY PROCESSES FOR GATE PATTERNING |
| 摘要 |
Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length. |
| 申请公布号 |
US2015145070(A1) |
申请公布日期 |
2015.05.28 |
| 申请号 |
US201414283168 |
申请日期 |
2014.05.20 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
SONG Stanley Seungchul;WANG Zhongze;YEAP Choh Fei |
| 分类号 |
H01L29/423;H01L21/28;H01L27/088 |
主分类号 |
H01L29/423 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for fabricating a plurality of devices on a die, comprising:
patterning a first region to create at least a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process, the first CPP being smaller than a single pattern lithographic limit; and patterning the first region to create a second gate having a second gate length or a second CPP with a second process, the second CPP being smaller than the single pattern lithographic limit, the second gate length being different than the first gate length. |
| 地址 |
San Diego CA US |
