Combined Transparent/Non-Transparent Cache

摘要

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

主权项

1. An apparatus comprising:
a tag memory having a first plurality of entries; a data memory having a second plurality of entries, wherein each of the first plurality of entries in the tag memory corresponds to an entry in a first subset of the second plurality of entries, and wherein ones of the second plurality of entries that are excluded from the first subset form a second subset of the second plurality of entries; and a control circuit coupled to the tag memory and the data memory, the control circuit configured to allocate a transparent memory within the first subset of the data memory, wherein a non-transparent memory is formed in the data memory from a combination of the second subset and a third subset of the second plurality of entries that are within the first subset but outside of the transparent memory.