Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands

摘要

A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

主权项

1. A semiconductor device comprising:
a first control circuit configured to produce a hit signal each time an internal refresh command is issued a predetermined number of times; a second control circuit configured to produce a control signal in response to the hit signal being produced, the control signal changing between first and second levels in response to temperature information indicative of a temperature of the semiconductor device; a memory cell array including a plurality of memory cells; an output buffer coupled to the memory cell array and configured to output data read from the memory cells; a calibration circuit coupled to the output buffer and configured to perform, when activated, a calibration operation on the output buffer to adjust an impedance of the output buffer; a refresh circuit coupled to the memory cell array and configured to perform a refresh operation on the memory cells of the memory cell array in response to the internal refresh command; and a third control circuit configured to issue the internal refresh command when the control signal takes the first level and to activate the calibration circuit in response to the hit signal when the control signal takes the second level.