发明名称 |
Clock and data recovery unit and power control method therefor and PON system |
摘要 |
In the present invention, wasted power consumption caused when a clock and data recovery unit in an optical network unit in a PON system is activated from a power-saving state is reduced and rapid, secure communication is performed. A clock and data recovery unit includes a phase-locked loop that can be set to normal mode or power-saving mode and that includes a voltage-controlled oscillator and recovers a clock signal and a data signal from input signals. The clock and data recovery unit includes a reference clock multiplier circuit that multiplies a reference clock signal and outputs the multiplied reference clock signal; and a frequency training loop that includes the same voltage-controlled oscillator and performs synchronous oscillation training by the voltage-controlled oscillator using the reference clock multiplier circuit before the phase-locked loop transitions from power-saving mode to normal mode. |
申请公布号 |
US9042737(B2) |
申请公布日期 |
2015.05.26 |
申请号 |
US201213985128 |
申请日期 |
2012.02.21 |
申请人 |
SUMITOMO ELECTRIC INDUSTRIES, LTD. |
发明人 |
Tanaka Naruto |
分类号 |
H04B10/00;H04L7/00;H03L7/08;H04B10/272;H04J3/06;H04W52/02;H04L7/033;H04J14/02 |
主分类号 |
H04B10/00 |
代理机构 |
Drinker Biddle & Reath LLP |
代理人 |
Drinker Biddle & Reath LLP |
主权项 |
1. A clock and data recovery unit used for optical communication using a burst signal, the clock and data recovery unit comprising:
a reference clock multiplier circuit that multiplies a reference clock signal and outputs a multiplied reference clock signal; a phase-locked loop that can be set to power-saving mode in addition to normal mode and that includes a voltage-controlled oscillator, the phase-locked loop recovering a clock signal and a data signal from input signals; and a frequency training loop that includes the voltage-controlled oscillator and performs synchronous oscillation training by the voltage-controlled oscillator using the reference clock multiplier circuit before the phase-locked loop transitions from the power-saving mode to the normal mode. |
地址 |
Osaka-shi, Osaka JP |