| 摘要 |
A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass gates. The first n-channel transistor, the first p-channel transistor, and the first enable transistor are connected in series between first and second reference potentials. The second n-channel transistor, the second p-channel transistor, and the second enable transistor are connected in series between the first and second reference potentials. The first pass gate is configured to selectively connect a first bitline to a first node. The first node is connected to a gate of the first n-channel transistor and a gate of the first p-channel transistor. The second pass gate is configured to selectively connect a second bitline to a second node. The second node is connected to a gate of the second n-channel transistor and a gate of the second p-channel transistor. |
| 主权项 |
1. A static random access memory (SRAM) cell comprising:
a first n-channel field-effect transistor (“n-channel transistor”); a second n-channel transistor; a first p-channel field-effect transistor (“p-channel transistor”); a second p-channel transistor; a first enable transistor, wherein the first n-channel transistor, the first p-channel transistor, and the first enable transistor are connected in series between a first reference potential and a second reference potential, and wherein the first enable transistor is located between the first n-channel transistor and the first p-channel transistor; a second enable transistor, wherein the second n-channel transistor, the second p-channel transistor, and the second enable transistor are connected in series between the first reference potential and the second reference potential, and wherein the second enable transistor is located between the second n-channel transistor and the second p-channel transistor; a first pass gate configured to selectively connect a first bitline to a first node, wherein the first node is connected to a gate of the first n-channel transistor and a gate of the first p-channel transistor, and wherein the first enable transistor is controlled by the first bitline; and a second pass gate configured to selectively connect a second bitline to a second node, wherein the second node is connected to a gate of the second n-channel transistor and a gate of the second p-channel transistor, and wherein the second enable transistor is controlled by the second bitline. |
