发明名称 Programmable resistive memory unit with multiple cells to improve yield and reliability
摘要 A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure.
申请公布号 US9042153(B2) 申请公布日期 2015.05.26
申请号 US201213590049 申请日期 2012.08.20
申请人 发明人 Chung Shine C.
分类号 G11C11/00;G11C11/56;G11C13/00;G11C17/16 主分类号 G11C11/00
代理机构 代理人
主权项 1. A programmable resistive memory, comprising: a plurality of programmable resistive memory units, at least a plurality of the programmable resistive memory units having at least one programmable resistive memory cells; each of the programmable resistive memory cells having a programmable resistive element and at least one diode, which serves as a program selector; the programmable resistive element in each of the programmable resistive memory cells has a first end coupled to a first supply voltage line, a second end coupled to a first terminal of the diode, and the second terminal of the diode coupled to a second supply voltage line; each of the programmable resistive memory cells being configured to program into a second logic state by applying a first voltage to the first supply voltage line and a second voltage to the second supply voltage line to turn on the diode serving as program selector; and the programmable resistive memory units being configured to store a second logic state if at least one of the programmable resistive memory cells corresponding thereto has a second logic state.
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