Techniques for wafer-level processing of QFN packages

摘要

Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

主权项

1. A process comprising:
forming at least one pillar over a semiconductor wafer; forming an encapsulation structure over the semiconductor wafer, the encapsulation structure at least substantially encapsulating the at least one pillar; etching the encapsulation structure to remove an outer section of the encapsulation structure so that a portion of the at least one pillar extends beyond the encapsulation structure; and applying a solder layer to the at least one pillar, the solder layer extending over at least part of a sidewall of the portion of the at least one pillar that extends beyond the encapsulation structure.