Method and apparatus for output of high-bandwidth debug data/traces in ICS and SoCs using embedded high speed debug

摘要

Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.

主权项

1. A method for debug testing of an electronic device, comprising: receiving debug data from a plurality of blocks; buffering the debug data in a buffer; operatively coupling an output of the buffer to at least one high-speed serial Input/Output (I/O) interface on the electronic device during debug test operations, wherein each of the at least one high-speed serial I/O interface is associated with a non-debug function during normal operation of the electronic device; and sending buffered debug data outbound from the electronic device via the at least one high-speed serial I/O interface, wherein at least one high-speed serial I/O interface comprises an HDMI port having a plurality of I/O pins, and wherein multiple lanes of serialized debug data is transferred from the HDMI port by sending differentiated signals over selected I/O pins from amongst the plurality of I/O pins.