Chip assembly with a coreless substrate employing a patterned adhesive layer

摘要

A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

主权项

1. A method of forming a bonded stack of a coreless substrate and a chip, said method comprising:
forming a stack, from bottom to top, of a stiffener, a patterned adhesive layer, and a coreless substrate layer including at least one coreless substrate integrally incorporated therein, wherein said patterned adhesive layer includes a plurality of holes therein; bonding at least one chip to said at least one coreless substrate; dicing said coreless substrate layer to isolate at least one bonded stack of a coreless substrate and a chip along vertical planes that include a closed periphery that does not overlie any area of said patterned adhesive layer; applying a blanket adhesive layer to a front side of said stiffener; and applying a photoresist to said blanket adhesive layer and lithographically patterning said photoresist.