发明名称 NON-VOLATILE SEMICONDUCTOR DEVICE
摘要 A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.
申请公布号 US2015138883(A1) 申请公布日期 2015.05.21
申请号 US201514607612 申请日期 2015.01.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIGA Hidehiro;SHIRAKAWA Masanobu
分类号 G11C16/14;G11C16/34;G11C16/04 主分类号 G11C16/14
代理机构 代理人
主权项 1. A non-volatile semiconductor device comprising: a plurality of memory cells stacked above a substrate, and connected in series between a first selecting transistor and a second selecting transistor; a plurality of word lines connected to control gates of the plurality of memory cells; a first selecting gate line connected to gate of the first selecting transistor and a second selecting gate line connected to gate of the second selecting transistor; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop including a plurality of erase operations, the plurality of erase operations including a first erase operation and a second erase operation, the control circuit being configured to apply a first voltage to one of the bit line and the source line and to apply a second voltage to one of the first selecting gate line and the second selecting gate line during the first erase operation, the control circuit being configured to apply a third voltage to one of the bit line and the source line and to apply a fourth voltage to one of the first selecting gate line and the second selecting gate line during the second erase operation, the third voltage being higher than the first voltage, the fourth voltage being substantially same as the second voltage.
地址 Tokyo JP