WORDLINE DECODER CIRCUITS FOR EMBEDDED CHARGE TRAP MULTI-TIME-PROGRAMMABLE-READ-ONLY-MEMORY

摘要

Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage. The switch includes a series of gated diodes from VWLL with a wordline low protection voltage of VWLL_PR generated by raising VWLL determined by the gated diodes by the threshold voltage, resulting in controlling the WL swing using thin-oxide devices.

主权项

1. A wordline decoder circuits controlling a charge trap behavior of an N-type MOSFET (NMOS) memory array having a plurality of rows and columns, comprising:
a driver for a wordline, wherein said driver comprises a first P-type MOSFET (PMOS), a second PMOS, a first NMOS, and second NMOS, a source and drain coupled serially in a predetermined order from a wordline high voltage (VWLH) to a wordline low voltage (VWLL), a decoder coupled to a gate of said first PMOS and the gate of said second NMOS to select one out of said plurality of rows in said memory array, wherein said first PMOS activates one out of said plurality of wordlines selected by said decoder to said VWLH, while keeping remaining wordlines deactivated with VWLL, and wherein said VWLH and said VWLL are controlled by a mode dependent voltage switch when in programming, and reset modes.