Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same

摘要

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

主权项

1. An integrated circuit, comprising:
a first cell configured to provide a logic function, the first cell configured in accordance with a first cell phasing, the first cell phasing defined by a first index value for conductive structure placements in a gate level and a second index value for conductive structure placements in a second interconnect level located two interconnect levels above the gate level, each of the first and second index values corresponding to a respective distance measured from a left boundary of the first cell and in a direction perpendicular to the left boundary of the first cell; and a second cell configured to provide a logic function, the second cell configured in accordance with a second cell phasing, the second cell phasing defined by a third index value for conductive structure placements in the gate level and a fourth index value for conductive structure placements in the second interconnect level, each of the third and fourth index values corresponding to a respective distance measured from a left boundary of the second cell and in a direction perpendicular to the left boundary of the second cell, wherein the second cell is positioned next to the first cell such that the left boundary of the second cell is aligned with a right boundary of the first cell, wherein the gate level of each of the first and second cells is defined by a first vertically oriented virtual grate, wherein the second interconnect level of each of the first and second cells is defined by a second vertically oriented virtual grate, wherein the first and second vertically oriented virtual grates are indexed to a common spatial location, wherein the first vertically oriented virtual grate is defined by a first grate pitch, and the second vertically oriented virtual grate is defined by a second grate pitch, wherein a ratio of the first grate pitch to the second grate pitch is defined by a rational number.