| 发明名称 |
METHOD AND CIRCUITRY FOR CONTROLLING A DEPLETION-MODE TRANSISTOR |
| 摘要 |
In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node. |
| 申请公布号 |
US2015137619(A1) |
申请公布日期 |
2015.05.21 |
| 申请号 |
US201414542962 |
申请日期 |
2014.11.17 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Seeman Michael Douglas;Bahl Sandeep R.;Anderson David I. |
| 分类号 |
H03K17/082;H02H3/00;H03K3/012 |
主分类号 |
H03K17/082 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. Circuitry for controlling a depletion-mode transistor, the circuitry comprising:
a first transistor having: a drain coupled to a source of the depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node; a second transistor having: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node; and a third transistor having: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node. |
| 地址 |
Dallas TX US |
