发明名称 パワースイッチのウェハ試験方法
摘要 A wafer test method of a power switch wherein a main IGBT and a current detecting IGBT that detects a current value of the main IGBT are integrally formed on the same semiconductor substrate is such that there is provided resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, the main IGBT and current detecting IGBT are energized simultaneously, thereby applying a constant current to a common collector terminal of the main IGBT and current detecting IGBT, and a current ratio (main current/detected current) between a main current of the main IGBT and a detected current of the current detecting IGBT is calculated from the current flowing through the current detecting IGBT, obtained from the voltage across the resistance means, and the constant current.
申请公布号 JP5720775(B2) 申请公布日期 2015.05.20
申请号 JP20130508788 申请日期 2012.02.17
申请人 富士電機株式会社 发明人 佐藤 茂樹
分类号 H01L21/66;H01L21/336;H01L27/04;H01L29/739;H01L29/78 主分类号 H01L21/66
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