Low speed access to DRAM

摘要

Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

主权项

1. An apparatus, comprising:
a memory array to store data; an output multiplexer to provide data to a read path; a serializer, coupled to the memory array and the output multiplexer, to receive data from the memory array, and provide data received from the memory array to the output multiplexer at a first speed; and an out of band access circuitry, coupled to the memory array and the output multiplexer, in parallel with the serializer, to receive data from the memory array, and provide data received from the memory array to the output multiplexer at a second speed, wherein the second speed is slower than the first speed.