System and method for containing analog verification IP

摘要

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

主权项

1. A method for containing analog verification intellectual property (IP) for circuit simulation, the method comprising:
using a computer, reading an analog verification file containing at least one analog verification unit (vunit) that contains properties describing analog circuit design verification requirements including checks for specified simulation results, wherein the analog verification file is separate from input design IP; binding the vunit to one of a top-level circuit, a subcircuit master, and a subcircuit instance during circuit hierarchy expansion, to set vunit scope; performing a circuit simulation with a computer-operated circuit simulation tool combining the input design IP and the analog circuit design verification requirements; and tangibly outputting circuit simulation and verification results.