| 摘要 |
<p>PROBLEM TO BE SOLVED: To efficiently determine a place to be parallelized for whichever purpose, parallelization for eliminating a delay fault or parallelization for improving power consumption.SOLUTION: A timing analysis unit 202 extracts a critical code block corresponding to a critical path from a plurality of code blocks. A circuit parallelization allowability analysis unit 203 excludes, from the plurality of code blocks, a non-parallelized code block that is not included among those to be circuit-parallelized and a code block following the non-parallelized code block, and specifies a parallelization candidate code block, including the critical code block, that is a candidate for circuit parallelization. A circuit parallelization determination unit 204 widens or narrows, centering on the critical code block, an evaluation object range that is a range of code blocks to be evaluated among the parallelization candidate code blocks and sets a plurality of evaluation object ranges, and selects an evaluation object range to be circuit-parallelized from among the plurality of evaluation object ranges.</p> |
