| 摘要 |
PROBLEM TO BE SOLVED: To provide an arithmetic circuit in which expansion in a circuit scale is suppressed and the occurrence of an arithmetic error is suppressed.SOLUTION: Provided is an arithmetic circuit to which at least two or more arithmetic blocks are connected, the arithmetic blocks comprising: correction means for correcting input data using correction data and generating corrected data; arithmetic means for performing an arithmetic process on the corrected data; selection means for selecting either the input data or the corrected data on which the arithmetic process was performed by the arithmetic means; and output means for generating output data and the correction data on the basis of the data selected by the selection means and the bit accuracy of the data used in arithmetic means of an other arithmetic block connected to the relevant arithmetic block, and outputting the generated output data and correction data to the other arithmetic block. The output means, as it generates the output data, truncates the data selected by the selection means so that the bit accuracy is ensured. |
